1. Field of the Invention
The present invention relates to a method and a memory circuit that can perform an initial calibration and a full time refresh mode calibration in the memory circuit, and particularly to a method and a memory circuit that can share in use an impedance matching circuit of the memory circuit to perform an initial calibration and a full time refresh mode calibration.
2. Description of the Prior Art
Communication between two chips not only needs an accurate timing, but also needs accurate impedance matching between the two chips. An extended mode register set (EMRS) mode can be utilized to perform an off chip driver impedance matching calibration to accurately design the impedance matching between the two chips according to a standard of the Joint Electron Device Engineering Council (JEDEC).
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a memory circuit 100 according to the prior art. After power is supplied to the memory circuit 100, the memory circuit 100 first enters the extended mode register set mode. In the extended mode register set mode, a user needs to utilize an oscilloscope to artificially determine slew rates of a logic-high voltage “1” and a logic-low voltage “0” of an output voltage of the memory circuit 100. Then, the user utilizes a pull-up driver 1022 and a pull-down driver 1024 of an impedance matching circuit 102 to adjust the slew rates of the logic-high voltage “1” and the logic-low voltage “0” of the output voltage of the memory circuit 100. In addition, as shown in FIG. 1, the memory circuit 100 further includes a calibration circuit 104 for adjusting strength of the slew rates.
However, as shown in FIG. 1, because the memory circuit 100 utilizes the impedance matching circuit 102 and the calibration circuit 104 to perform the extended mode register set mode and the full time refresh mode calibration, respectively, the memory circuit 100 has a larger area and the memory circuit 100 can not perform the refresh mode calibration full time.